1. Technical Field
The invention relates generally to computer-aided design of integrated circuits, and more particularly, to the optimization of a digital circuit based on yield considerations. Even more particularly, the invention relates to the computation of yield gradients using statistical timing.
2. Background Art
Variability in integrated circuits increases with each new technology generation. Sources of variability include manufacturing conditions, device fatigue, environmental variations, and phase-locked loop (PLL) variations.
In the past, static timing analyses have been used to determine the performance of a circuit. In static timing analysis, a circuit is mapped to a graph called a timing graph. The longest path through the timing graph is the performance-limiting (i.e., critical) path of the circuit. If the delay of the critical path is more than a required value, the circuit cannot function properly. That is, the circuit has a timing violation. Because of variability, only a fraction of all manufactured circuits can meet the required timing constraints. This fraction is called the parametric yield of the circuit.
Typically, a static timing analysis is conducted for a particular setting of each of the process and environmental parameters, such as the thickness of a metal layer, the lengths of transistors, temperature, supply voltage, etc. The set of values to which process parameters are assigned is called a process corner. Such a static timing analysis at a particular process corner is referred to as “deterministic” timing analysis.
Deterministic timing analysis only verifies timing at a few selected process corners. Because of variability, multiple deterministic timing analyses are generally required to accurately analyze a circuit. When a large number of independently variable process parameters must be modeled, the number of timing runs necessary using traditional deterministic static timing analysis makes such a method impractical. Optimization of circuits based on deterministic timing analysis is also problematic. In the presence of process variations, the critical path is no longer unique. In fact, each process corner may have a different critical path. Thus, guiding optimization by the results of a deterministic timing analysis may not be the most efficient way to optimize a circuit.
These problems are partially overcome by statistical or probabilistic timing analysis, as taught in Patent Application Publication No. 20050065765 to Visweswariah, which is hereby incorporated by reference. In such an analysis, timing quantities such as delays, arrival times, and slacks are not treated as single numbers, but as correlated probability distributions. As such, the full probability distribution of the performance of the circuit under the influence of variations is predicted by a single timing run.
In such a run, the statistical maximum of the delay of all paths of the circuit is predicted. This quantity is called “statistical circuit delay.” It is to be noted that this quantity is not the delay of any particular path. Rather, it represents the statistical maximum of the delay of all paths of the circuit.
In addition to timing analysis, an important role of a static timing analyzer is to provide diagnostics that are useful for optimization of the circuit. Such optimization may be automated or manual, and discrete or continuous. Since the critical path is not unique, as explained above, diagnostics that cover the entire space of process variations are especially important. The concept of criticality was taught in Patent Application Publication No. 20050066298 to Visweswariah, which is hereby incorporated by reference. Simply defined, the criticality probability of an edge, node, or path of a timing graph is the probability of manufacturing a chip in which the edge, node or path is in the critical path. An efficient method of computing criticality probabilities of all edges of a timing graph was also taught in U.S. Patent Application Publication No. 20050066298.
Recently, a method for computing the sensitivity of the mean of the circuit's longest path to the mean or nominal delay of each circuit component was taught in “Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations” by Xin Li et al the IEEE International Conference on Computer-Aided Design, San Jose, Calif., November 2005. Unfortunately, this method does not compute yield gradients, and the sensitivities are computed by an inefficient chain-ruling method that propagates sensitivities through the timing graph.
Recently, a method for computing sensitivities in the context of statistical timing was taught by K. Chopra et al., “Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation,” at the International Conference on Computer-Aided Design, San Jose, Calif., November 2005. While this approach uses the concept of a cutset, it uses a numerical perturbation method for sensitivity computation, which is neither efficient nor accurate.
While criticality computation and sensitivity analysis provide valuable diagnostics, they still do not provide sufficient data for fully optimizing a circuit. More efficient optimization may be achieved if one were to know the gradient of a parametric yield (i.e., the circuit's yield due to variation in process parameters) with respect to the delay characteristics of one or more circuit components, e.g., the delay of each gate or the size of each transistor. To this extent, a need exists for a method for determining the gradient of a parametric yield relative to the delay characteristics or designable parameters of a circuit component.